1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor integrated circuit (IC) device, and more particularly to a Bi-CMOS semiconductor IC device including bipolar transistors and MOS FETs.
2. Description of the Prior Art
Prior art methods of manufacturing Bi-CMOS IC devices are disclosed, for example, in the paper entitled "Dependency on A Surface Oxide Film to Phosphorus Diffusion" in the preliminary reports (Lecture No. 416) of the Fifth Scientific Lecture Meeting of the Society of Japanese Applied Physics, in autumn 1984, and in the paper entitled "A Gate Oxidation Effect on Bipolar elements by a Bi-CMOS Process" in a separate volume 1, Part 90 of the lecture papers at the National Meeting in a Communication Section of the Society of Electronic Communication held in 1984.
As shown in FIG. 3, it is desirable that the bipolar transistor region of a Bi-CMOS IC device has a flat PN junction between its emitter and base regions 5A and 6A in an epitaxial layer over a P-type silicon substrate 10 to obtain a controlled transconductance hFE.
In a conventional Bi-CMOS IC process, a thick oxide layer formed on the surface of a silicon substrate is selectively removed to form contact windows to the base and emitter regions, and then a thin oxide layer is formed in the windows. If the thick oxide layer is formed through a single photolithographic process, it tends to be horizontally eaten during an etching process, whereby the window obtained is degraded in the accuracy of its dimensions. For this reason, two different photolithographic steps are generally performed to form windows having a slow sloped wall in the thick oxide layer which can provide good step coverage for wiring layers.
For example, in order to form a sloped window, a thick silicon oxide layer formed over a silicon substrate is selectively removed to form a larger window exposing a surface of a diffused region, and then a thin silicon oxide layer (ex. gate oxide layer) is formed in the larger window. Next, the thin silicon oxide layer is selectively removed to form a smaller window for electrical contact in the larger window.
However, the additional oxidation process after the formation of the larger window will deeply rediffuse the impurities in the emitter region into the base region due to the accelerated diffusion effect of the thin silicon oxide layer formed on the surface of the emitter region in the larger window.
As a result, as shown in FIGS. 4 and 5, a protruded or recessed PN junction plane is formed between the base region 5A and the emitter region 6A over the silicon substrate 10. This has made it difficult to obtain a bipolar transistor region having a controlled transconductance h.sub.FE and higher breakdown voltage characteristics between the base and emitter regions.